Presentation at Advanced Packaging International 2026 are grouped into 6 key themes which collectively provide complete coverage of the global packaging industry.
If you are interested in speaking at Advanced Packaging International 2026, please contact [email protected] or call +44 (0)24 7671 8970.
The artificial intelligence induced compute explosion demands new technology and solutions at all system-levels. Advanced packaging concepts bring processing and memory chips closer together, enabling higher performance and better power-efficiency. For longer intra-system communication, pluggable optics is now a well-established solution. Co-packaging the optical modules with the processing and memory chips on the same substrate increases the overall bandwidth and improves power efficiency but also comes with assembly and integration challenges. This presentation will focus on photonic chip-to-fiber interfacing technology, scalability, density and compatibility with electrical assembly processes. The critical optical properties will be discussed.
As the semiconductor industry moves toward heterogeneous integration, advanced packaging is indispensable for improving system performance. The rising complexity calls for a holistic approach that links innovation with scalable processes. Central are expanding lab-to-industry initiatives and collaborative research–industry consortia. By fostering tight ties between cutting-edge research and early industrial adoption, these platforms accelerate the transfer of disruptive technologies—such as 3D packaging and glass-panel packaging—from concept to high-volume manufacturing. They reduce early-stage risks by broadening access to shared infrastructure and top-tier expertise. This work highlights the bi-directionality of innovation and transfer, promoting a feedback loop that extends beyond traditional models. By channeling industrial insights on process instabilities, yield issues, and scalability challenges back into research, activities can be precisely aligned with real-world manufacturing needs. This ensures applied research targets the most pressing bottlenecks and accelerates actionable outcomes. For Europe, pilot lines hosted by FMD institutes within the APECS framework demonstrate that bidirectional knowledge transfer is feasible and ready to address modern semiconductor challenges.
Gordon Moore predicted a “Day of Reckoning.” That day has arrived. Transistor sizes are approaching handfuls of atoms and while shrinks still continue, their benefits in economics, speed, and effective chip size have ground to a halt. However, as Moore predicted, there is another path forward that doesn’t rely on ever-shrinking devices. Advanced packaging is the new path, and it is at the core of the new industry model that is Foundry 2.0. Foundry 2.0 brings together the best of all technologies and material solutions by using the interconnect and manufacturing methods typically used in building semiconductor devices themselves. This foundry evolution, based on Advanced Packaging (AP), it is inherently a different business than today’s foundry model. This talk will discuss Foundry 2.0, the AP tool box and how the new AP centric foundry model leverages application specific systems of chiplets for cost reduction and innovation.
The rapid growth of bandwidth demand in data centers and high-performance computing is accelerating the adoption of integrated photonics and co-packaged optics (CPO). This presentation examines how heterogeneous integration using 2.5D and 3D packaging architectures enables tight integration of photonic devices with advanced logic and memory. Key challenges in scaling photonic integration to high-volume manufacturing—including optical alignment, thermal management, electrical–optical co-design, and yield—are discussed. The talk highlights process and packaging innovations that support reliable, cost-effective deployment of co-packaged photonic systems.
As transistor scaling faces physical and economic limits, heterogeneous integration is emerging as a key enabler for advanced computing systems. By tightly integrating logic, memory, accelerators, and advanced interconnect technologies within a single package, heterogeneous integration enables scalable performance, improved energy efficiency, and architectural flexibility beyond monolithic designs. This presentation will explore how advanced packaging, chiplet architectures, and high bandwidth electrical and optical interconnects address the growing demands of artificial intelligence and datacentric workloads. Heterogeneous integration provides a practical path to extend system level scaling and unlock next generation computing architectures beyond Moore’s Law.
As advanced packaging outpaces front-end scaling, heterogeneous integration demands interconnects with higher density, larger routing area, and more efficient manufacturing processes. Syenta’s Localized Electrochemical Metallization (LEM) is a maskless, additive copper (and other metals) patterning method that enables 1 µm line/space interconnects on 300 mm wafers and panels (including organic substrates) while eliminating 30-50% SAP and damascene steps. By directly transferring patterns through a localized electrochemical process, LEM supports large-area RDL without reticle stitching, critical for chiplet-based AI/HPC architectures and HBM integration. With this platform, addressing the AI Memory Wall becomes a reality. Modern AI accelerators are limited not by compute, but by data movement. HBM-to-logic bandwidth scaling is now dominated by RDL density limits. LEM’s fine-pitch, large-area metallization provides 5–10× higher bandwidth density, directly alleviating this bottleneck and enabling larger multi-die systems. LEM reduces interconnect process complexity by 30–50% and accelerates cycle time by ~40%. The presentation highlights recent achievements in density, area, and mixed-CD structures, along with the roadmap toward sub-micron multilayer integration.
As traditional transistor scaling faces economic, power, and physical limits, performance leadership in advanced computing is increasingly defined at the system level. Modern AI and high-performance systems are now constrained less by compute capability and more by data movement, power delivery, thermal management, and integration efficiency. This presentation explores how advanced packaging has evolved from a back-end manufacturing step into a first-order performance enabler. By enabling millimeter-scale interconnects, heterogeneous integration, and chiplet-based architectures, advanced packaging allows logic, memory, power, and I/O to be optimized independently while operating as a single system. Through system-level observations from recent AI and high-performance designs, the talk highlights why packaging choices now directly impact energy efficiency, yield economics, and sustained performance. The session concludes by examining why co-optimization across silicon, packaging, materials, and system architecture has become essential for continued scaling - and what this shift means for the future structure of computing.
Awaiting presentation abstract.
The industry’s move toward increasingly large and complex package architectures is accelerating the transition from wafer level to panel level substrates. This shift is driven not only by the demand for improved substrate utilization, but also by the rapid rise of heterogeneous integration, where multiple functional dies—logic, memory, RF, photonics, or power devices—are co packaged into advanced system in package (SiP) platforms. As these heterogeneous assemblies grow in size and functionality, traditional wafer formats reach their physical and economic limits, making panel formats essential. While established panel sizes like 510 × 515 mm and 600 × 600 mm remain widely adopted, newer compact formats such as the 310 × 310 mm are gaining traction. This format offers substantially improved substrate utilization compared to a 300 mm wafer and enables partial reuse of existing wafer-level manufacturing equipment, providing an attractive path for scaling fan out technologies. As heterogeneous integration drives higher I/O densities and more complex RDL structures, the demands on deposition and pre treatment processes also intensify. For high performance computing (HPC) applications such as AI accelerators, GPUs, and advanced logic, reliable sputter deposition of redistribution layer (RDL) seed layers, typically using titanium–copper (Ti Cu) stacks, becomes critical. At the same time, package level thermal challenges continue to escalate, requiring highly uniform backside metallization (BSM) films to ensure efficient heat spreading and secure attachment of heat sinks or heat spreaders. Both RDL seed layer and BSM processes must be compatible with panel substrates that contain significant fractions of polymer-based materials. These materials trap moisture and volatiles, which can compromise adhesion, film integrity, and long-term reliability. To meet the yield and throughput requirements of mass production, effective degassing becomes a key enabler. The presentation will explain how Evatec combines advanced degas, etch, and PVD process technologies, to support the highlighted applications.
As the semiconductor industry transitions toward heterogeneous integration and Fan-Out Wafer-Level Packaging (FOWLP), manufacturers face significant process challenges that traditional mask-based lithography cannot easily address. Specifically, the unpredictable nature of die shift, substrate warpage, and severe surface topography often leads to overlay errors and yield loss1. This presentation explores the transformative advantages of direct-write Laser Beam Lithography (LBL) as a maskless solution tailored for these complexities. We will discuss how eliminating physical masks facilitates rapid prototyping, enabling immediate design adjustments and significantly accelerating development cycles in R&D and small batch production environments. Next, we will demonstrate how RAITHs LBL technology transcends the resolution limits of mask aligners, achieving feature sizes down to 500 nm for high-density interconnects. Beyond resolution, a key focus will be RAITHs hybrid autofocus strategy, which enables perfect writing over highly topological and warped substrates with over 600 μm range. Moreover, RAITHs LBL employs die-by-die alignment algorithms to dynamically distort exposure patterns, compensating for individual die misplacement.
Discover how AEMtec transformed from an IDM into a leading specialized OSAT, carving out a unique position in the European semiconductor landscape. While industry roadpaths often follow rigid lines, AEMtec thrives on complexity: we build custom-specific package designs that lay the groundwork for future technologies. Our presentation highlights a unique process portfolio powered by state-of-the-art equipment. We bridge the gap between high-end backend services - including Wafer Test, UBM, RDL, and Dicing - and precision assembly such as High-Accuracy Die Bonding, Flip Chip, and Wire Bond. The final edge: integrating these packages into large-scale systems under the highest cleanliness and vacuum standards (Grade 1 & 2) for global market leaders.
Advanced packaging is essential for enabling system performance, resilience and high value product architectures. As complexity grows, the challenge is not only innovation but translating new concepts into scalable, repeatable manufacturing. This presentation examines how aligning technology choices, process readiness and collaborative development supports industry in advancing new concepts towards production. Key topics include bridging prototypes to stable, high yield production, selecting bonding, assembly and interconnect strategies that support rapid scale-up, and deploying flexible platforms that embed design for manufacture and reliability. The talk also highlights how medium volume manufacturing provides a controlled environment to mitigate adoption risks, shorten learning cycles and provide OEMs and system integrators earlier access to advanced packaging capabilities.
The UK or in fact Europe cannot compete with the Far East / China for high volume advanced semiconductor packaging. However, there are multiple applications whereby annual quantities are much smaller, but still complex semiconductor packaging is required. This presentation will cover annual quantities ranging from 10off – 500,000off per annum with advanced packaging covering 3D Heterogenous integration, RF devices, wafer bumping for medical devices, SiC & GaN power device packaging and high Cu wirebond count devices for AI processor manufacture. All these technologies are being developed and manufactured in the UK with European OEM and chip start partners.
In advanced packaging, resist strip is a repeat step across RDL, UBM, wafer-level bumping and rework, where residue and contamination directly impact yield and reliability. This talk assesses a practical alternative to piranha and solvent strip: ozone gas diffused through heated deionised water in an ozone rich, high temperature environment. Tool data shows complete removal, throughput comparable to legacy chemistries, reduced downstream contamination, and over 70% lower CO2e per wafer.
Wide bandgap semiconductors such as GaN and SiC offer step-change improvements in power density and efficiency, but conventional packaging increasingly limits their performance. This paper presents a panel-level embedded die packaging platform developed by RAM Innovations to address parasitic inductance, thermal management, and scalability challenges. RAM has built a number of power module demonstrators using these packaging techniques showing >50% loop inductance reduction, lower switching losses, reduced EMI, and improved thermal spreading compared to conventional assemblies. The panel-level approach enables parallel, high-volume manufacture while maintaining performance advantages.
As photonics moves closer to compute in AI data centers , display engines shrink for AR form factors, and quantum technologies push toward scalable systems, photonics packaging is becoming a decisive market-growth enabler. Start-ups are proving silicon photonics functions across communications, computing, and sensing—but these breakthroughs will only become products if they can be packaged with high-volume, manufacturable approaches. In parallel, foundries and assembly houses are ramping dedicated platforms and PDKs to support emerging photonic architectures, exemplified by initiatives like TSMC’s COUPE within the broader CoWoS ecosystem. Spanning die integration (2.5D/3D), fiber coupling, encapsulation, and testing, photonics packaging faces stricter tolerances and multi-physics constraints than microelectronics, yet must ultimately adopt microelectronics-style repeatability, yield control, and process integration to scale—driving new requirements across wafer-level processing, bonding, precision etch/deposition, and test, and making ecosystem-wide orchestration by foundries, OSATs, and platform owners essential. This talk will review the trends for photonics packaging, the industrial landscape and market forecasts.
Efficient thermal management, particularly at the packaging level, is becoming increasingly crucial for high-power-density electronic devices. The heat spreader, onto which the semiconductor die is directly attached, is a key component of the package. Ideally, it should have high thermal conductivity while maintaining a compatible coefficient of thermal expansion (CTE). Metal diamond composites are promising candidates, as both their CTE and the thermal conductivity can be tailored to suit specific application. In this talk, we will present a comparative study of the thermal performance of metal-diamond composite heat spreaders versus standard materials, using frequency domain thermal reflectance, Raman thermography measurements, and finite element thermal simulations. We will also highlight the importance of the thermal interface materials (TIMs) in the overall thermal behavior of the package.
As device power densities continue to rise in AI, HPC, and power electronics, thermal management has become one of the most pressing bottlenecks in advanced packaging. Diamond, with its unmatched thermal conductivity, high bandgap and radiation hardness, offers a unique pathway to overcome these challenges. This talk will highlight recent advances in integrating synthetic diamond into advanced packaging — from heat spreaders and chip-carriers to on-die caps — enabling significant reductions in hotspot temperatures and improvements in energy efficiency. Potential applications will be discussed for both data centers, where cooling demands are escalating, and space electronics, where thermal reliability under extreme conditions is mission-critical.
Progress in advanced electronic and functional devices is limited by rigid conventional thin-film processes, which restrict flexibility for spatially localized, multi-material fabrication. ATLANT 3D’s Direct Atomic Layer Processing (DALP®) enables digitally controlled, atomic-scale deposition of multiple materials in a single workflow, eliminating the need for intermediate lithography. DALP’s programmable architecture supports rapid materials discovery and direct device manufacturing, allowing precise control over material placement, thickness, and interfaces. This technology expands nanoscale fabrication capabilities, providing a streamlined path from materials exploration to manufacturable, device-ready structures for advanced semiconductor and functional applications.
The production of semiconductor components (chips) is realized on thin wafers and is an energy and resource-intensive process that can take up to 12 weeks. Before the chips can be further processed, they must be separated on the wafer by the so-called dicing - a critical process step that introduces considerable damage to the chip frontside, backside and sidewalls. The market development of recent years combined with the AI boom leads to a high demand for computing power and data storage, e.g. for training of AI models and in consequence leads to a steady increase in energy consumption. To counteract rising energy consumption, innovative, more efficient product designs, e.g. HBM, are required. These are mostly achieved by a broader use of modern packaging methods e.g. Advanced Packaging and Hybrid Bonding. Unfortunately, these modern packaging and bonding methods lead to an increasing demand on chip quality and cleanliness, which cannot be achieved with most of the currently used dicing methods. As a result, semiconductor manufacturers have to utilize complex multi-step separation processes, including plasma dicing, which are not only expensive but also consume a large amount of chemical process gases. Our innovative LidroCUT® process based on USP lasers in liquid overcomes these challenges. The liquid binds the emerging particles leading to a debris free surface and contamination free sidewalls, enabling hybrid bonding without additional cleaning steps. Meanwhile, the cooling capacity of the liquid allows for a precise laser power use, leading to high quality edges and high break strength.
The semiconductor industry is entering an era defined by unprecedented performance demands, driven by AI, quantum computing, hyperscale data centers, and EV growth. Addressing these inflection points requires lithography solutions that can go beyond the limits of conventional optical and single-beam e-beam technologies. In this presentation, we introduce the world’s first high-productivity multi-column e-beam lithography systems designed for fab production. With large depth of focus, wide field of view, ultra-high resolution, and adaptable patterning capabilities, Multibeam systems enable device makers to achieve novel, performance-optimized system architectures across various growing applications, including advanced packaging, quantum, compound semiconductors/power devices, silicon photonics, rapid prototyping and more. In advanced packaging—where performance, power efficiency, and yield are paramount—our systems are enabling the transition to advanced heterogeneous integration at wafer scale, and rapid production of purpose-built chips. This new generation of packaging allows chip-to-chip interconnects to approach on-chip interconnect performance, enabling an ~10× reduction in latency, ~40× improvement in bandwidth density, and ~100× improvement in transfer-energy-per-bit. Multibeam can also be leveraged to accelerate critical technologies like backside power delivery and provide higher-yielding alternatives to bridge-die approaches, paving the way for scalable, manufacturable heterogeneous integration. Discover how Multibeam’s multi-column e-beam lithography is reshaping the path forward for the most demanding semiconductor applications and enabling high-density Advanced Integration at the Leading Edge, today.
Optical metrology has long been a key enabler in semiconductor manufacturing. As AI and HPC drive demand for performance, bandwidth, and energy efficiency, the industry is rapidly advancing packaging technologies such as 2.5D/3D integration, chiplets, panel-level packaging, and hybrid bonding. These next-generation architectures introduce increasingly complex three-dimensional structures, tighter tolerances, and new material combinations. Pushing conventional inspection methods to their limits and requiring optical metrology to evolve alongside these developments. This presentation explores how advanced optical metrology addresses these challenges and enables the development and production of next-generation semiconductor packages. Measurement approaches for key process steps will be highlighted, demonstrating how high-resolution surface metrology provides precise characterization of complex structures while improving process insight, control, and yield. In addition, the presentation illustrates how modern optical metrology supports reliable device integration and extends its value across further stages of the semiconductor manufacturing process.
As conventional semiconductor scaling approaches physical and economic limits, performance gains are increasingly achieved through optimised packaging architectures rather than smaller transistors alone. Advancements in co-packaged optics and heterogeneous integration, for example, enables the combination of diverse technologies such as logic, memory, photonics, sensors, and advanced materials to be assembled within a compact single system, placing new demands on package design, assembly strategy, and process control. This presentation explores how packaging architecture decisions directly influence system performance, yield, reliability, scalability, and time-to-market. It provides practical insight into the challenges of assembling complex systems and the methods used to optimise alignment and placement accuracy, bonding parameters and thermal/ mechanical stability. Emphasis is placed on modular, adaptable platforms that support evolving architectures and enable rapid process development from R&D to production. Attendees will gain a clearer understanding of how modular bonding and assembly technologies are used where current architectures are encounter limitations, and which solutions are proving effective in real development and production environments. The session will also highlight key factors shaping future packaging roadmaps and provide a foundation for technical discussion on designing architectures that balance performance, manufacturability, and flexibility.
Inkjet printing is emerging as a scalable additive technology for semiconductor manufacturing, particularly in advanced back end processes. It enables precise, digital deposition of functional materials such as photoresists and polyimides, offering an efficient alternative to conventional spin coating and photolithography. Selective inkjet deposition allows uniform coating over complex topographies—including cavities and edges—while significantly reducing material consumption and waste, especially for costly resists. The ability to deposit material only where needed, with adjustable thickness and real time pattern adaptation, enhances process control and supports device customization. Printing and exposure results from various materials will be presented. Further applications include MEMS and power semiconductor fabrication, where inkjet printed resists enable patterning without photolithography. This streamlines process flows and supports ESG objectives by lowering chemical usage and energy demand. The system architecture accommodates flexible substrate formats, from wafers to large IC substrates, and contributes to cost efficient, flexible, and environmentally responsible semiconductor production.
As AI systems extend into sensing and physical interaction, photonic packaging requirements shift toward scalable heterogeneous integration, optical power handling, and manufacturability. We present a silicon photonics (SiPh) packaging platform for multi-wavelength light sources targeting external light source (ELS) and sensing applications. The platform uses a cantilever-based assembly method that enables deterministic integration of arbitrary materials onto SiPh. Cantilevers self-align during placement and are assembled using standard pick-and-place tools with 2–3 µm accuracy in 16 optical connections per placement without sub-micron active alignment. Large cross-section waveguides relax CD tolerances by >10× while supporting optical power densities exceeding 5 × 10⁷ W/cm², enabling a high-yield, manufacturable packaging solution for ELS, spectrometers, and LiDAR.
As photonic integration advances toward scalable, high-throughput manufacturing, the integration of active devices—particularly lasers— remains a key challenge. Vanguard Automation addresses this with our unique solution of photonic wire bonds and facet-attached micro-lenses, which are fabricated in-situ at chip-level and can be applied to both batch processing and wafer level integration. This solution leverages 3D nano-printing technology to fabricate freeform optical structures with sub-micron precision which eliminate the need for active alignment, while enabling robust, low-loss, high-yield photonic interconnects. Vanguard Automation’s solution is uniquely positioned to meet industry demands, lighting the way for scalable next-generation photonic integration.
Due to rising costs of advanced nodes and the challenges of downscaling analog and I/O signals, single-die architectures are giving way to alternatives such as system-in-package (SIP), 2.5D, 3D, chiplet-on-interposer, and fan-out wafer-level packaging. The main challenges are to boost chip-to-chip bandwidth, integrate more functions, and reduce power consumption—all at a reasonable cost. This requires rethinking the traditionally siloed supply chain and co-optimizing system and technology from the outset of component design. Sectors such as automotive and high-performance computing (HPC) will soon rely on advanced packaging to enable simpler, faster, and more cost-effective chip designs with enhanced performance and versatility. CEA-Leti is a technology research institute of CEA, a pioneer RTO in micro and nanotechnologies that tailors differentiated application solutions to ensure competitiveness in a wide range of markets. The Institute addresses critical challenges such as healthcare, energy, transport and information and communication technologies (ICT). It offers a competitive packaging platform for 8” and 12” wafers that is aligned with the “More than Moore” roadmap. Its areas of expertise include silicon interposers, hybrid bonding, high-density TSV, 3D technology, and Fan Out Wafer Level Packaging. This presentation aims to provide an overview of CEA-Leti’s latest advancements in advanced 3D and heterogeneous integration.
Awaiting presentation abstract.
We are in an exciting era of silicon photonics technology and packaging, where photonic integrated circuits (PICs) are heterogeneously assembled with both electronic integrated circuits (EICs) and a broad range of optical components. Packaging technologies such as micro-transfer printing enable the integration of III–V lasers, amplifiers, and high-speed modulators, with optical connectivity provided by printed microlenses and photonic wire bonds. In parallel, hybrid bonding and through-silicon vias are enabling dense 3D EIC–PIC integration. To capitalize on these advances at the system level, designers need standardized assembly data, rules, and models that capture both the physical and behavioral views of the interfaces across domains. The AIM Photonics’ Assembly Design Kit (ADK) provides this enablement through layout automation, design rules, electrical and optical models, simulation workflows, and prototype boards. By integrating the ADK with the AIM Photonics design PDK, we create a seamless path from PIC design to packaged prototypes. Our goal is to make advanced packaging accessible to a broader design community and accelerate system innovation for next-generation applications.
Awaiting presentation abstract.
The packaging area includes a large number of different process steps. The creation of a redistribution layer is only one example, and it is not a single simple process. It consists of several steps such as lithography, development, metal etching, photoresist stripping, and cleaning. Each of these steps typically requires dedicated equipment, which increases complexity, footprint, and cost in the fab. With Siconnex, multiple process steps can be integrated into one system, with a strong focus on metal etching and photoresist strip. This integration reduces the need for separate tools and supports higher productivity and efficiency in semiconductor packaging manufacturing.
From the worldwide pandemic to current geopolitical tensions the need for alternative supply chains has never been so relevant. Amkor Technology Portugal (ATEP) is Europe´s biggest Advanced Packaging Outsourced Semiconductor Assembly and Test provider. ATEP supports an ample range of Advanced packaging techniques, and is uniquely positioned to support the Europe centric advances in Foundry technologies. Amkor´s unique Hybrid Panel Technology engineering line enables innovative die first and die last FanOut packaging for a range of applications.
Photonic integrated circuits are becoming an integral part of package-level semiconductor systems. A range of electronic-photonic integration strategies is being explored to serve diverse functionalities and markets. Assembly and packaging technologies developed enable dense integration of photonics, electronics, and micro-optics in a small form factor on a common substrate, while supporting efficient scaling for volume production environments. Along with these, test processes and tools for functional verification of the final packages and validation of subsequent assembly steps are being established. Convergence with existing semiconductor standards and the enablement of efficient design are essential for a wide adoption of such heterogeneous technologies. An example of a design flow featuring a heterogeneous process design kit created for the PhotonicLEAP glass-based electronic-photonic packaging technology, compliant with a JEDEC standard, will be demonstrated.
In recent decades, semiconductors have become increasingly vital to everyday life, evolving from enabling analog applications (such as early computers and mobile phones) to powering today’s on demand world of data centers, smartphones, and tablets. As we enter a new era, their influence will expand even further into the robotics domain—driven by AI from cloud to edge and by smart, connected devices. For these technologies, miniaturization—traditionally governed by front end processes and advanced wafer nodes—will be essential. In recent years, electronic packaging has gained significant importance, not only for achieving further miniaturization but also for ensuring cost efficiency. In fact, packaging is poised to enable and accelerate this emerging robotics era through heterogeneous integration, making it a cornerstone for future innovation. With heterogeneous integration, packaging and front end technology must be closely aligned to deliver true system level solutions. To operate effectively at the edge, such systems must be capable of sensing, thinking, connecting, and acting. Ensuring the proper functionality of these systems requires a deep understanding of their behavior—both throughout manufacturing and over their full operational lifetime. Achieving this demands careful material selection based on material characteristics, supported by detailed thermo mechanical and thermal modeling to guarantee optimal performance. This presentation will illustrate these concepts using examples from the field.
Micro-transfer printing (MTP) enables the integration of diverse materials and devices, such as III-V and LiNbO3 components, onto a single platform. With high alignment accuracy and efficient use of source material, MTP facilitates cutting-edge photonic integrated circuits (PICs), all while maintaining compatibility with existing manufacturing workflows. We will elaborate on the status of the TRANSVERSE pilot line that develops this technology on 200mm wafer silicon photonics wafers.
The space sector is becoming increasingly competitive, with continuous demands for higher performance and lower overall costs from mission inception through to end-of-life decommissioning. These pressures influence all levels of system development, including the selection and procurement of individual components and subsystems. In parallel with this trend, electrical, electronic, and photonics components originally designed for terrestrial applications—such as those used in the automotive and telecommunications sectors—have demonstrated high reliability when manufactured in large volumes and qualified under established industrial standards (e.g., AEC-Q automotive qualification standards). The use of commercial off-the-shelf (COTS) components offers many advantages for space and similar high-reliability applications, most notably improved availability, reduced cost, and high performance. However, concerns remain regarding the long-term reliability of these components when operating in the harsh conditions of the space environment. This presentation reports on the results of detailed reliability evaluations performed on families of electronic and photonics COTS components by Tyndall National Institute under several contracts with the European Space Agency. The results demonstrate promising performance for certain component types—particularly automotive electronics—while also indicating that further manufacturing improvements and increased standardisation are required for others.
o The European semiconductor ecosystem is undergoing a major transformation as Europe seeks to strengthen its technological sovereignty and competitiveness in advanced microelectronics. A key element of this effort is improving access to chip design capabilities for researchers, startups, SMEs, and industrial innovators. The European Chip Design Platform (EuroCDP), developed within the framework of the Chips Joint Undertaking and coordinated by imec, aims to address this challenge. EuroCDP provides a comprehensive infrastructure that facilitates access to advanced electronic design automation (EDA) tools, design IP, training resources, and semiconductor design expertise. By lowering barriers to entry for chip design, the platform supports innovation across Europe and enables a broader community to participate in the development of next-generation semiconductor technologies. Building on Europe’s long-standing experience with initiatives such as Europractice, EuroCDP seeks to scale and modernise the ecosystem supporting chip design. The platform strengthens Europe’s design capabilities, fosters collaboration between academia and industry, and accelerates the path from research to market. Ultimately, EuroCDP plays a strategic role in supporting Europe’s ambitions under the European Chips Act.
Awaiting presentation abstract.
