Presentation at Advanced Packaging International 2026 are grouped into 6 key themes which collectively provide complete coverage of the global packaging industry.
If you are interested in speaking at Advanced Packaging International 2026, please contact [email protected] or call +44 (0)24 7671 8970.
The semiconductor industry is entering an era defined by unprecedented performance demands, driven by AI, quantum computing, hyperscale data centers, and EV growth. Addressing these inflection points requires lithography solutions that can go beyond the limits of conventional optical and single-beam e-beam technologies. In this presentation, we introduce the world’s first high-productivity multi-column e-beam lithography systems designed for fab production. With large depth of focus, wide field of view, ultra-high resolution, and adaptable patterning capabilities, Multibeam systems enable device makers to achieve novel, performance-optimized system architectures across various growing applications, including advanced packaging, quantum, compound semiconductors/power devices, silicon photonics, rapid prototyping and more. In advanced packaging—where performance, power efficiency, and yield are paramount—our systems are enabling the transition to advanced heterogeneous integration at wafer scale, and rapid production of purpose-built chips. This new generation of packaging allows chip-to-chip interconnects to approach on-chip interconnect performance, enabling an ~10× reduction in latency, ~40× improvement in bandwidth density, and ~100× improvement in transfer-energy-per-bit. Multibeam can also be leveraged to accelerate critical technologies like backside power delivery and provide higher-yielding alternatives to bridge-die approaches, paving the way for scalable, manufacturable heterogeneous integration. Discover how Multibeam’s multi-column e-beam lithography is reshaping the path forward for the most demanding semiconductor applications and enabling high-density Advanced Integration at the Leading Edge, today.
As the semiconductor industry moves toward heterogeneous integration, advanced packaging is indispensable for improving system performance. The rising complexity calls for a holistic approach that links innovation with scalable processes. Central are expanding lab-to-industry initiatives and collaborative research–industry consortia. By fostering tight ties between cutting-edge research and early industrial adoption, these platforms accelerate the transfer of disruptive technologies—such as 3D packaging and glass-panel packaging—from concept to high-volume manufacturing. They reduce early-stage risks by broadening access to shared infrastructure and top-tier expertise. This work highlights the bi-directionality of innovation and transfer, promoting a feedback loop that extends beyond traditional models. By channeling industrial insights on process instabilities, yield issues, and scalability challenges back into research, activities can be precisely aligned with real-world manufacturing needs. This ensures applied research targets the most pressing bottlenecks and accelerates actionable outcomes. For Europe, pilot lines hosted by FMD institutes within the APECS framework demonstrate that bidirectional knowledge transfer is feasible and ready to address modern semiconductor challenges.
The rapid growth of bandwidth demand in data centers and high-performance computing is accelerating the adoption of integrated photonics and co-packaged optics (CPO). This presentation examines how heterogeneous integration using 2.5D and 3D packaging architectures enables tight integration of photonic devices with advanced logic and memory. Key challenges in scaling photonic integration to high-volume manufacturing—including optical alignment, thermal management, electrical–optical co-design, and yield—are discussed. The talk highlights process and packaging innovations that support reliable, cost-effective deployment of co-packaged photonic systems.
As transistor scaling faces physical and economic limits, heterogeneous integration is emerging as a key enabler for advanced computing systems. By tightly integrating logic, memory, accelerators, and advanced interconnect technologies within a single package, heterogeneous integration enables scalable performance, improved energy efficiency, and architectural flexibility beyond monolithic designs. This presentation will explore how advanced packaging, chiplet architectures, and high bandwidth electrical and optical interconnects address the growing demands of artificial intelligence and datacentric workloads. Heterogeneous integration provides a practical path to extend system level scaling and unlock next generation computing architectures beyond Moore’s Law.
As advanced packaging outpaces front-end scaling, heterogeneous integration demands interconnects with higher density, larger routing area, and more efficient manufacturing processes. Syenta’s Localized Electrochemical Metallization (LEM) is a maskless, additive copper (and other metals) patterning method that enables 1 µm line/space interconnects on 300 mm wafers and panels (including organic substrates) while eliminating 30-50% SAP and damascene steps. By directly transferring patterns through a localized electrochemical process, LEM supports large-area RDL without reticle stitching, critical for chiplet-based AI/HPC architectures and HBM integration. With this platform, addressing the AI Memory Wall becomes a reality. Modern AI accelerators are limited not by compute, but by data movement. HBM-to-logic bandwidth scaling is now dominated by RDL density limits. LEM’s fine-pitch, large-area metallization provides 5–10× higher bandwidth density, directly alleviating this bottleneck and enabling larger multi-die systems. LEM reduces interconnect process complexity by 30–50% and accelerates cycle time by ~40%. The presentation highlights recent achievements in density, area, and mixed-CD structures, along with the roadmap toward sub-micron multilayer integration.
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As traditional transistor scaling faces economic, power, and physical limits, performance leadership in advanced computing is increasingly defined at the system level. Modern AI and high-performance systems are now constrained less by compute capability and more by data movement, power delivery, thermal management, and integration efficiency. This presentation explores how advanced packaging has evolved from a back-end manufacturing step into a first-order performance enabler. By enabling millimeter-scale interconnects, heterogeneous integration, and chiplet-based architectures, advanced packaging allows logic, memory, power, and I/O to be optimized independently while operating as a single system. Through system-level observations from recent AI and high-performance designs, the talk highlights why packaging choices now directly impact energy efficiency, yield economics, and sustained performance. The session concludes by examining why co-optimization across silicon, packaging, materials, and system architecture has become essential for continued scaling - and what this shift means for the future structure of computing.
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As the semiconductor industry transitions toward heterogeneous integration and Fan-Out Wafer-Level Packaging (FOWLP), manufacturers face significant process challenges that traditional mask-based lithography cannot easily address. Specifically, the unpredictable nature of die shift, substrate warpage, and severe surface topography often leads to overlay errors and yield loss1. This presentation explores the transformative advantages of direct-write Laser Beam Lithography (LBL) as a maskless solution tailored for these complexities. We will discuss how eliminating physical masks facilitates rapid prototyping, enabling immediate design adjustments and significantly accelerating development cycles in R&D and small batch production environments. Next, we will demonstrate how RAITHs LBL technology transcends the resolution limits of mask aligners, achieving feature sizes down to 500 nm for high-density interconnects. Beyond resolution, a key focus will be RAITHs hybrid autofocus strategy, which enables perfect writing over highly topological and warped substrates with over 600 μm range. Moreover, RAITHs LBL employs die-by-die alignment algorithms to dynamically distort exposure patterns, compensating for individual die misplacement.
Efforts to implement green technologies in semiconductor manufacturing have historically been slow with acceptance. Nowhere is this more apparent than in photoresist stripping, where aggressive chemistries remain standard, despite their well-documented environmental burdens. This paper presents a comprehensive assessment of a novel process that offers a rare and timely exception: chemical-free resist removal using ozone gas diffused through heated deionized water. Unlike ozone-dissolved water systems this method operates in a high-temperature, ozone-rich gas environment. The result is rapid, surface-driven chemical deconstruction of the resist polymer, eliminating the need for persistent oxidizers or solvents, while producing minimal downstream contamination. Measured CO₂e emissions per wafer are reduced by over 70% relative to sulfuric-peroxide and solvent-based strip methods. Tool-level performance data confirms comparability with common process chemistries, complete resist removal, and throughput on par with legacy methods. The paper will substantiate environmental advantages based on documented chemical usage rates for conventional and ozone-based strip processes. It will then confirm the technical soundness of the method - grounding its effectiveness in known reaction pathways and supporting it with fab-level data on resist removal, compatibility, and defectivity. Together, these findings show that the process can be deployed now - without trade offs - to meet rising green manufacturing demands.
The UK or in fact Europe cannot compete with the Far East / China for high volume advanced semiconductor packaging. However, there are multiple applications whereby annual quantities are much smaller, but still complex semiconductor packaging is required. This presentation will cover annual quantities ranging from 10off – 500,000off per annum with advanced packaging covering 3D Heterogenous integration, RF devices, wafer bumping for medical devices, SiC & GaN power device packaging and high Cu wirebond count devices for AI processor manufacture. All these technologies are being developed and manufactured in the UK with European OEM and chip start partners.
Wide bandgap semiconductors such as GaN and SiC offer step-change improvements in power density and efficiency, but conventional packaging increasingly limits their performance. This paper presents a panel-level embedded die packaging platform developed by RAM Innovations to address parasitic inductance, thermal management, and scalability challenges. RAM has built a number of power module demonstrators using these packaging techniques showing >50% loop inductance reduction, lower switching losses, reduced EMI, and improved thermal spreading compared to conventional assemblies. The panel-level approach enables parallel, high-volume manufacture while maintaining performance advantages.
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Efficient thermal management, particularly at the packaging level, is becoming increasingly crucial for high-power-density electronic devices. The heat spreader, onto which the semiconductor die is directly attached, is a key component of the package. Ideally, it should have high thermal conductivity while maintaining a compatible coefficient of thermal expansion (CTE). Metal diamond composites are promising candidates, as both their CTE and the thermal conductivity can be tailored to suit specific application. In this talk, we will present a comparative study of the thermal performance of metal-diamond composite heat spreaders versus standard materials, using frequency domain thermal reflectance, Raman thermography measurements, and finite element thermal simulations. We will also highlight the importance of the thermal interface materials (TIMs) in the overall thermal behavior of the package.
As device power densities continue to rise in AI, HPC, and power electronics, thermal management has become one of the most pressing bottlenecks in advanced packaging. Diamond, with its unmatched thermal conductivity, high bandgap and radiation hardness, offers a unique pathway to overcome these challenges. This talk will highlight recent advances in integrating synthetic diamond into advanced packaging — from heat spreaders and chip-carriers to on-die caps — enabling significant reductions in hotspot temperatures and improvements in energy efficiency. Potential applications will be discussed for both data centers, where cooling demands are escalating, and space electronics, where thermal reliability under extreme conditions is mission-critical.
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Due to rising costs of advanced nodes and the challenges of downscaling analog and I/O signals, single-die architectures are giving way to alternatives such as system-in-package (SIP), 2.5D, 3D, chiplet-on-interposer, and fan-out wafer-level packaging. The main challenges are to boost chip-to-chip bandwidth, integrate more functions, and reduce power consumption—all at a reasonable cost. This requires rethinking the traditionally siloed supply chain and co-optimizing system and technology from the outset of component design. Sectors such as automotive and high-performance computing (HPC) will soon rely on advanced packaging to enable simpler, faster, and more cost-effective chip designs with enhanced performance and versatility. CEA-Leti is a technology research institute of CEA, a pioneer RTO in micro and nanotechnologies that tailors differentiated application solutions to ensure competitiveness in a wide range of markets. The Institute addresses critical challenges such as healthcare, energy, transport and information and communication technologies (ICT). It offers a competitive packaging platform for 8” and 12” wafers that is aligned with the “More than Moore” roadmap. Its areas of expertise include silicon interposers, hybrid bonding, high-density TSV, 3D technology, and Fan Out Wafer Level Packaging. This presentation aims to provide an overview of CEA-Leti’s latest advancements in advanced 3D and heterogeneous integration.
The packaging area includes a large number of different process steps. The creation of a redistribution layer is only one example, and it is not a single simple process. It consists of several steps such as lithography, development, metal etching, photoresist stripping, and cleaning. Each of these steps typically requires dedicated equipment, which increases complexity, footprint, and cost in the fab. With Siconnex, multiple process steps can be integrated into one system, with a strong focus on metal etching and photoresist strip. This integration reduces the need for separate tools and supports higher productivity and efficiency in semiconductor packaging manufacturing.
