PRESENTATION


Thin Film Deposition Developments for Large Size Packages on Panel Scale

The industry’s move toward increasingly large and complex package architectures is accelerating the transition from wafer level to panel level substrates. This shift is driven not only by the demand for improved substrate utilization, but also by the rapid rise of heterogeneous integration, where multiple functional dies—logic, memory, RF, photonics, or power devices—are co packaged into advanced system in package (SiP) platforms. As these heterogeneous assemblies grow in size and functionality, traditional wafer formats reach their physical and economic limits, making panel formats essential. While established panel sizes like 510 × 515 mm and 600 × 600 mm remain widely adopted, newer compact formats such as the 310 × 310 mm are gaining traction. This format offers substantially improved substrate utilization compared to a 300 mm wafer and enables partial reuse of existing wafer-level manufacturing equipment, providing an attractive path for scaling fan out technologies. As heterogeneous integration drives higher I/O densities and more complex RDL structures, the demands on deposition and pre treatment processes also intensify. For high performance computing (HPC) applications such as AI accelerators, GPUs, and advanced logic, reliable sputter deposition of redistribution layer (RDL) seed layers, typically using titanium–copper (Ti Cu) stacks, becomes critical. At the same time, package level thermal challenges continue to escalate, requiring highly uniform backside metallization (BSM) films to ensure efficient heat spreading and secure attachment of heat sinks or heat spreaders. Both RDL seed layer and BSM processes must be compatible with panel substrates that contain significant fractions of polymer-based materials. These materials trap moisture and volatiles, which can compromise adhesion, film integrity, and long-term reliability. To meet the yield and throughput requirements of mass production, effective degassing becomes a key enabler. The presentation will explain how Evatec combines advanced degas, etch, and PVD process technologies, to support the highlighted applications.

Andre Schenk

Evatec


André Schenk (Technical Marketing Manager) has a background in semiconductor engineering and received a diploma degree in electrical engineering from TU Ilmenau in 1997. He was working in several positions at Infineon Technologies as process and development engineer. Later on, he worked as sales engineer for Silfine, Evatec and Materion Optics. Today he is responsible for the technical sales support at Evatec Europe GmbH covering the whole range of Evatecs portfolio.