Recent Developments in Advanced Heterogeneous 3D Integration at the Wafer Level

Due to rising costs of advanced nodes and the challenges of downscaling analog and I/O signals, single-die architectures are giving way to alternatives such as system-in-package (SIP), 2.5D, 3D, chiplet-on-interposer, and fan-out wafer-level packaging. The main challenges are to boost chip-to-chip bandwidth, integrate more functions, and reduce power consumption—all at a reasonable cost. This requires rethinking the traditionally siloed supply chain and co-optimizing system and technology from the outset of component design. Sectors such as automotive and high-performance computing (HPC) will soon rely on advanced packaging to enable simpler, faster, and more cost-effective chip designs with enhanced performance and versatility. CEA-Leti is a technology research institute of CEA, a pioneer RTO in micro and nanotechnologies that tailors differentiated application solutions to ensure competitiveness in a wide range of markets. The Institute addresses critical challenges such as healthcare, energy, transport and information and communication technologies (ICT). It offers a competitive packaging platform for 8” and 12” wafers that is aligned with the “More than Moore” roadmap. Its areas of expertise include silicon interposers, hybrid bonding, high-density TSV, 3D technology, and Fan Out Wafer Level Packaging. This presentation aims to provide an overview of CEA-Leti’s latest advancements in advanced 3D and heterogeneous integration.